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18-mbit burst of 2 pipelined sram with qdr? architecture preliminary cy7c1303cv25 cy7c1306cv25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-44701 rev. *b revised july 31, 2009 features separate independent read and write data ports ? supports concurrent transactions 167 mhz clock for high bandwidth ? 2.5 ns clock-to-valid access time 2-word burst on all accesses double data rate (ddr) interfaces on both read and write ports (data transferred at 333 mhz) at 167 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for ou tput data (c and c ) to minimize clock skew and flight time mismatches single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes 2.5v core power supply with hstl inputs and outputs available in 165-ball fbga package (13 x 15 x 1.4 mm) variable drive hstl output buffers expanded hstl output voltage (1.4v?1.9v) jtag interface variable impedance hstl configurations cy7c1303cv25 ? 1m x 18 cy7c1306cv25 ? 512k x 36 functional description the cy7c1303cv25 and cy7c1306cv25 are 2.5v synchronous pipelined srams, equipped with qdr? architecture. qdr architecture consists of two separate ports: the read port and the write port to access the memory array. the read port has data outputs to support read operations and the write port has data inputs to support write operations. qdr architecture has separate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common i/o devices. access to each port is accomplished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of the k clock. accesses to the qdr read and write ports are completely independent of one another. all accesses are initiated synchronously on the rising edge of the positive input clock (k). to maximize data throughput, both read and write ports are provided with ddr interfaces. therefore, data can be transferred into the device on every rising edge of both input clocks (k and k ) and out of the device on every rising edge of the output clock (c and c , or k and k when in single clock mode) thereby maximizing performance while simplifying system design. each address location is associated with two 18-bit words (cy7c1303cv25), or 36-bit words (cy7c1306cv25) that burst sequentially into or out of the device. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k/k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide description 167 mhz unit maximum operating frequency 167 mhz maximum operating current 500 ma [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 2 of 21 logic block diagram (cy7c1303cv25) logic block diagram (cy7c1306cv25) 512k x 18 array clk a (18:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 18 19 36 18 bws [1:0] v ref write add. decode write reg 18 a (18:0) 19 q [17:0] 18 18 18 write reg c c 512k x 18 array 256k x 36 array clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 36 18 72 36 bws [3:0] v ref write add. decode write reg 36 a (17:0) 18 q [35:0] 36 36 36 write reg c c 256k x 36 array [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 3 of 21 pin configuration the pin configurations for cy 7c1303cv25 and cy7c1306cv25 follow. 165-ball fbga (13 x 15 x 1.4 mm) pinout cy7c1303cv25 (1m x 18) 1 2 3 4 5 6 7 8 9 10 11 a nc gnd/144m nc/36m wps bws 1 k nc rps a gnd/72m nc b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss aaav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h nc v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdo tck a a a c aaatmstdi cy7c1306cv25 (512k x 36) 1 2 3 4 5 6 7 8 9 10 11 a nc gnd/288m nc/72m wps bws 2 k bws 1 rps nc/36m gnd/144m nc b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss aaav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h nc v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdo tck a a a c aaatmstdi [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 4 of 21 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals. sampled on the rising edge of k and k clocks during valid write operations. cy7c1303cv25 - d [17:0] cy7c1306cv25 - d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deas serting deselects the write port. deselecting the write port ignores d [x:0] . bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. cy7c1303cv25 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] . cy7c1306cv25 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] ,bws 2 controls d [26:18] and bws 3 controls d [35:27]. bytes not written remain unaltered. deselecting a byt e write select ignores the corresponding byte of data and it is not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k clock during active read operations and on the rising edge of k for write operations. these address inputs are multiplexed for both read and write operations. internally, the devic e is organized as 1m x 18 (2 arrays each of 512k x 18) for cy7c1303cv25 and 512k x 36 (2 arrays each of 256k x 36) for cy7c1306cv 25. therefore, only 19 address inputs are needed to access the entire memory array of cy7c1303cv25 and 18 address inputs for cy7c1306cv25. these inputs are ignor ed when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations, or k and k when in single clock mode. when the read port is deselected, q [x:0] are automatically tri-stated. cy7c1303cv25 ? q [17:0] cy7c1306cv25 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting deselects the read port. when deselected, the pending access is allowed to complete and the output drivers are aut omatically tri-stated follow ing the next rising edge of the c clock. each read access consists of a burst of two sequential transfers. c input clock positive input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 7 for further details. c input clock negative input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 7 for further details. k input clock positive input clock input . the rising edge of k is used to c apture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. q [x:0] output impedance are set to 0.2 x rq, wher e rq is a resistor connected between zq and ground. alternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connect ed directly to gnd or left unconnected. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 5 of 21 tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/36m n/a not connected to the die . can be tied to any voltage level. gnd/72m input address expansion for 72m. this pin must be tied to gnd on cy7c1303cv25. nc/72m n/a address expansion for 72m. this pin can be tied to any voltage level on cy7c1306cv25. gnd/144m input address expansion for 144m. this pin must be tied to gnd on cy7c1303cv25/cy7c1306cv25. gnd/288m input address expansion for 288m. this pin must be tied to gnd on cy7c1306cv25. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 6 of 21 functional overview the cy7c1303cv25 and cy7c1306cv25 are synchronous pipelined burst srams equipped with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and flows out through the read port. these devices multiplex the address inputs to minimize the number of address pins required. by having separate read and write ports, the qdr completely eliminates the need to ?turn-around? the data bus and avoids any possible data contention, thereby simplifying system design. each access consists of two 18-bit data transfers in the case of cy7c1303cv25, and two 36-bit data transfers in the case of cy7c1306cv25 in one clock cycle. accesses for both ports are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the output clocks (c and c, or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks (c and c or k and k when in single clock mode). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1303cv25 is described in the following sections. the same basic descriptions apply to cy7c1306cv25. read operations the cy7c1303cv25 is organized internally as two arrays of 512k x 18. accesses are completed in a burst of two sequential 18-bit data words. read operatio ns are initiated by asserting rps active at the rising edge of t he positive input clock (k). the address is latched on the rising edge of the k clock. the address presented to the address inputs is stored in the read address register. following the next k clock rise the corresponding lowest order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c , the next 18-bit data word is driven onto the q [17:0] . the requested data is valid 2.5 ns from the rising edge of the output clock (c and c or k and k when in single clock mode). synchronous internal circuitry aut omatically tri-states the outputs following the next rising edge of the positive output clock (c). this allows a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the same k clock rise, the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the address is latched and the information presented to d [17:0] is stored into the write data register, provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. when deselected, the write port ignores all inputs after completion of pending write operations. byte write operations byte write operations are sup ported by the cy7c1303cv25. a write operation is initiated as described in the section write operations on page 6. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each 18-bit data word. asserting the appropriate by te write select input during the data portion of a write latches the data being presented and writes it into the device. deas serting the byte write select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read, modify, or wr ite operations to a byte write operation. single clock mode the cy7c1303cv25 can be used with a single clock that controls both the input and output registers. in this mode, the device recognizes only a single pa ir of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if t he device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power on. this func tion is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1303cv25 operate independently of one another. as each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the tran saction on the other port. the user can start reads and writes in the same clock cycle. if the ports access the same location at the same time, the sram delivers the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. depth expansion the cy7c1303cv25 has a port select input for each port. this enables for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 and 350 , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 7 of 21 application example figure 1 shows four qdr-i used in an application. figure 1. application example truth table the truth table for cy7c1303cv25 and cy7c1306cv25 follows. [1, 2, 3, 4, 5, 6] operation k rps wps dq dq write cycle: load address on the rising edge of k ; input write data on k and k rising edges. l-h x l d(a + 0) at k(t) d(a + 1) at k (t) read cycle: load address on the rising edge of k; wait one cycle; read data on c and c rising edges. l-h l x q(a + 0) at c(t + 1) q(a + 1) at c (t + 1) nop: no operation l-h h h d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state vt = vddq/2 cc# d a k cc# d a k bus master (cpu or asic) sram #1 sram #4 data in data out address rps# wps# bws# source k source k# delayed k delayed k# r = 50 ohms r = 250 ohms r = 250 ohms r p s # w p s # b w s # r p s # w p s # b w s # vt vt vt r r r zq q k# zq q k# notes 1. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 2. device powers up deselected with the outputs in a tri-state condition. 3. ?a? represents address location latched by the devices when tr ansaction was initiated. a + 0, a + 1 represents the internal a ddress sequence in the burst. 4. ?t? represents the cycle at which a read/write operation is star ted. t + 1 is the first clock cycle succeeding the ?t? clock cycle. 5. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 6. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but per mits most rapid restart by overcoming transmission line charging symmetrically. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 8 of 21 write cycle descriptions the write cycle description tabl e for cy7c1303cv25 follows. [1, 7] bws 0 bws 1 k k comments l l l?h ? during the data portion of a write sequence , both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence , both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a wr ite sequence, only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a wr ite sequence, only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. write cycle descriptions the write cycle description tabl e for cy7c1306cv25 follows. [1, 7] bws 0 bws 1 bws 2 bws 3 k k comments l l l l l?h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l?h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h h l?h ? no data is written into the device during this portion of a write operation. h h h h ? l?h no data is written into the device during this portion of a write operation. note 7. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. bws 0 , bws 1 , bws 2, and bws 3 can be altered on different portions of a write cycle, as long as the set up and hold requirements are achieved. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 9 of 21 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 11. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 14). the output changes on the falling edge of tck. tdo is connected to the least signific ant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 12. upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow the fault isolation of the boar d level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is l oaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 15 shows the order in which the bits are connected. each bi t corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in identification register definitions on page 14. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in instruction codes on page 14. three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instruc tions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shifted in, the tap controller must be moved into the update-ir state. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 10 of 21 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction re gister. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded in to the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is supplied during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap contro ller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instructio n is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pi ns. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates t hat the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?e xtest output bus tri-state,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is pre-set high to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 11 of 21 tap controller state diagram the state diagram for the tap controller follows. [8] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 8. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 12 of 21 tap controller block diagram tap electrical characteristics over the operating range [9, 10, 11] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.7 v i x input and output load current gnd v i v dd ?5 5 a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 9. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 10. overshoot: v ih (ac) < v ddq + 0.85v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5v (pulse width less than t cyc /2). 11. all voltage referenced to ground. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 13 of 21 tap ac switching characteristics over the operating range [12, 13] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 10 ns t tdis tdi setup to tck clock rise 10 ns t cs capture setup to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions figure 2 shows the tap timing and test conditions. [13] figure 2. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 gnd 1.25v 50 2.5v 0v all input pulses 1.25v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 12. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 13. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 14 of 21 identification register definitions instruction field value description cy7c1303cv25 cy7c1306cv25 revision number (31:29) 000 000 version number. cypress device id (28:12) 01011011010010101 010 11011010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00 000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring c ontents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 15 of 21 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 26n 299g 566a 831j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 57r 329f 594a 863j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 14 11n 41 9d 68 1b 95 1n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 17 11l 44 9b 71 1d 98 2n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 21 11k 48 9a 75 2e 102 4r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 16 of 21 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied.. ?55c to +125c supply voltage on v dd relative to gnd ........?0.5v to +3.6v supply voltage on v ddq relative to gnd.......?0.5v to +v dd dc applied to outputs in high-z ........ ?0.5v to v ddq + 0.5v dc input voltage [10] .............................. ?0.5v to v dd + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, m. 3015).. > 2001v latch-up current ................................................... > 200 ma operating range range ambient temperature (t a ) v dd [14] v ddq [14] commercial 0c to +70c 2.5 0.1v 1.4v to 1.9v industrial ?40c to +85c electrical characteristics dc electrical characteristics over the operating range [11] parameter description test conditions min typ max unit v dd power supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage 1.4 1.5 1.9 v v oh output high voltage note 15 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 16 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [10] v ref + 0.1 v ddq + 0.3 v v il input low voltage [10, 17] ?0.3 v ref ? 0.1 v v ref input reference voltage [18] typical value = 0.75v 0.68 0.75 0.95 v i x input leakage current gnd v i v ddq ? 5 5 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i dd [19] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 500 ma i sb1 automatic power down current max v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 240 ma ac electrical characteristics over the operating range parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v notes 14. power up: assumes a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 15. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ohms <= rq <= 350 ohms. 16. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ohms <= rq <= 350 ohms. 17. this spec is for all inputs except c and c clock. for c and c clock, v il (max.) = v ref ? 0.2v 18. v ref (min) = 0.68v or 0.46v ddq , whichever is larger, v ref (max) = 0.95v or 0.54v ddq , whichever is smaller. 19. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 17 of 21 capacitance tested initially and after any design or process change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v, v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7 pf thermal resistance tested initially and after any design or process change that may affect these parameters. parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 16.7 c/w jc thermal resistance (junction to case) 6.5 c/w figure 3. ac test loads and waveforms 1.25v 0.25v r = 50 5pf including jig and scope all input pulses device r l = 50 z 0 = 50 v ref = 0.75v v ref = 0.75v [20] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 (b) rq = 250 20. unless otherwise noted, test conditions are based on signal tran sition time of 2v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 18 of 21 switching characteristics over the operating range [20] cypress parameter consortium parameter description 167 mhz unit min max t power v dd (typical) to the first access read or write [21] 10 s cycle time t cyc t khkh k clock and c clock cycle time 6.0 ns t kh t khkl input clock (k/k and c/c ) high 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 2.7 3.3 ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0 2.0 ns setup times t sa t sa address setup to clock (k/k ) rise 0.7 ? ns t sc t sc control setup to clock (k/k ) rise (rps , wps , bws 0 , bws 1 )0.7?ns t sd t sd d [x:0] setup to clock (k/k ) rise 0.7 ? ns hold times t ha t ha address hold after clock (k/k ) rise 0.7 ? ns t hc t hc control hold after clock (k/k ) rise (rps , wps , bws 0 , bws 1 )0.7?ns t hd t hd d [x:0] hold after clock (k/k ) rise 0.7 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 2.5 ns t doh t chqx data output hold after output c/c clock rise (active to active) 1.2 ? ns t chz t chz clock (c/c ) rise to high-z (active to high-z) [22, 23] ?2.5ns t clz t clz clock (c/c ) rise to low-z [22, 23] 1.2 ? ns notes 21. this part has a voltage regulator that steps down the voltage internally; t power is the time that the power is supplied above v dd minimum initially before a read or write operation is initiated. 22. t chz , t clz , are specified with a load capacit ance of 5 pf as in part (b) of ac test loads and waveforms . transition is measured 100 mv from steady state voltage. 23. at any voltage and temperature t chz is less than t clz and t chz less than t co . [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 19 of 21 switching waveforms figure 4. switching waveforms [24, 25, 26] read read write write p o n e t i r w p o n e t i r w d a e r k 1 8 5 4 3 2 1 0 6 7 k rps w ps a q d c c a1 a0 d10 t kh t khkh t khch t co t kl t cyc thc t sa t ha t hd t khch dont care undefined t clz t chz tsc t kh t kl a2 a3 a4 a5 a6 t ha d11 d30 d31 d50 d51 d60 d61 t sd t hd 1 2 q 0 0 q 1 4 q 0 4 q 0 2 q 1 0 q t co t doh t doh t khkh tcyc 9 t sa t sd notes 24. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0+1. 25. outputs are disabled (high-z) one clock cycle after a nop. 26. in this example, if address a0 = a1, then data q00 = d10 and q01 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. [+] feedback
preliminary cy7c1303cv25 cy7c1306cv25 document #: 001-44701 rev. *b page 20 of 21 ordering information not all of the speed, package and temperature ranges are avai lable. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 167 CY7C1303CV25-167BZC 51-85180 165-ball fine pitc h ball grid array (13 x 15 x 1.4 mm) commercial cy7c1306cv25-167bzc cy7c1303cv25-167bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1306cv25-167bzxc cy7c1303cv25-167bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1306cv25-167bzi cy7c1303cv25-167bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1306cv25-167bzxi package diagram figure 5. 165-ball fbga (13 x 15 x 1.4 mm) a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180a [+] feedback
document #: 001-44701 rev. *b revised july 31, 2009 page 21 of 21 qdr rams and quad data rate rams comprise a new family of products developed by cypress, hitachi, idt, nec, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. preliminary cy7c1303cv25 cy7c1306cv25 ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems applic ation implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document history page document title: cy7c1303cv25/cy7c1306cv25, 18-mbit burst of 2 pipelined sram with qdr? architecture document number: 001-44701 rev. ecn no. submission date orig. of change description of change ** 2192568 see ecn vkn/pyrs new datasheet *a 2507779 see ecn vkn/pyrs corrected jtag id code *b 2746930 07/31/09 njy post to external web site [+] feedback

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